#ifndef IRQ_H
#define IRQ_H


#include "xscugic.h"
#include "xil_exception.h"


/*
* 中断优先级共32级，0最高，248最低，每级数值相差8
* 0, 8, 16, 32, 40 ..., 248.
*/
#define PRIORITY_LEVEL_0    0U
#define PRIORITY_LEVEL_1    8U
#define PRIORITY_LEVEL_2    16U
#define PRIORITY_LEVEL_3    24U
#define PRIORITY_LEVEL_4    32U
#define PRIORITY_LEVEL_5    40U
#define PRIORITY_LEVEL_6    48U
#define PRIORITY_LEVEL_7    56U
#define PRIORITY_LEVEL_8    64U
#define PRIORITY_LEVEL_9    72U
#define PRIORITY_LEVEL_10   80U
#define PRIORITY_LEVEL_11   88U
#define PRIORITY_LEVEL_12   96U
#define PRIORITY_LEVEL_13   104U
#define PRIORITY_LEVEL_14   112U
#define PRIORITY_LEVEL_15   120U
#define PRIORITY_LEVEL_16   128U
#define PRIORITY_LEVEL_17   136U
#define PRIORITY_LEVEL_18   144U
#define PRIORITY_LEVEL_19   152U
#define PRIORITY_LEVEL_20   160U
#define PRIORITY_LEVEL_21   168U
#define PRIORITY_LEVEL_22   176U
#define PRIORITY_LEVEL_23   184U
#define PRIORITY_LEVEL_24   192U
#define PRIORITY_LEVEL_25   200U
#define PRIORITY_LEVEL_26   208U
#define PRIORITY_LEVEL_27   216U
#define PRIORITY_LEVEL_28   224U
#define PRIORITY_LEVEL_29   232U
#define PRIORITY_LEVEL_30   240U
#define PRIORITY_LEVEL_31   248U


/* IRQ中断类型
* Trigger is the new trigger type for the IRQ source.
* Each bit pair describes the configuration for an INT_ID.
* SFI    Read Only    b10 always
* PPI    Read Only    depending on how the PPIs are configured.
*                    b01    Active HIGH level sensitive
*                    b11 Rising edge sensitive
* SPI                LSB is read only.
*                    b01    Active HIGH level sensitive
*                    b11 Rising edge sensitive/
*/
#define IRQ_TYPE_HIGH_LEVEL  1U
#define IRQ_TYPE_PEDGE       3U

#define CPU0_ID  0
#define CPU1_ID  1

extern XScuGic scuGic;


// 初始化中断控制器
int scuGic_Inti(XScuGic *scuGicPtr, u16 scuGicID);
//scuGic_Inti(&scuGic, XPAR_SCUGIC_0_DEVICE_ID);


// 设置中断优先级与类型，关联中断处理函数并启用对应ID的中断源
void scuGic_Set_ConnectAndEnable(XScuGic *scuGicPtr, u32 Int_Id, u8 Priority, u8 Trigger,
		                         Xil_ExceptionHandler X_Handler,  void *CallBackRef);
//scuGic_Set_ConnectAndEnable(&scuGic, Int_Id, PRIORITY_LEVEL_3, IRQ_TYPE_PEDGE,
//		                      X_Handler, X_Handler_CallBackRef);


// 指定哪个CPU来处理对应ID的中断
void XScuGic_InterruptMaptoCpu(XScuGic *scuGicPtr, u8 Cpu_Id, u32 Int_Id);
//XScuGic_InterruptMaptoCpu(&scuGic, CPU1_ID, Int_Id);


#endif
